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Location: Sunnyvale, California

Job Description:

• Design and verify synthesizable verilog modules for mixed-signal ASIC.
• Interact with DSP architects to translate functionality into RTL for synthesis using standard CMOS libraries.
• Write test vectors for verifying functionality.

Qualifications:

• BS in Electrical Engineering with 3-7 years experience

Experience Requirements:

• Extensive hands on experience in coding synthesizable verilog RTL modules required.
• Candidates should have a throrough knowledge of Verilog language as well practical experience in writing modules from a functional hardware description provided by DSP architects.
• Experience with simulation tools such as Cver or ModelSim is expected.
• Job responsibilities will also include interacting with a back-end team to ensure proper functionality of the synthesized netlist as well as providing proper timing closure.
• Should be able to quickly ramp up to analyze and add to an existing design code base.
• Candidate should also have working knowledge of digital testing to add scan paths for DFT as well as create test vectors to provide adequate test coverage for verifying the design.
• Knowledge of operating in a Linux environment is expected.